Simplified check node processing in non-binary LDPC decoder
US11290128B2 · kind B2 · utility
0Cited by
0References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Jul 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/658
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.