Full adder cell with improved power efficiency
US11294631B2 · kind B2 · utility
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3References
20Claims
0Family size
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Key dates
| Filing date | Oct 23, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Oct 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.