System and method of obtaining multiple factor performance gain in processing system

US11294709B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Maik Brett · Schweinhub, DE
• Sidhartha Taneja · New Delhi, IN
• Christian Tuschen · Munich, DE
• Tejbal Prasad · Greater Noida, IN
• Nikhil Tiwari · Pala, IN
• Saurabh Arora · Gurugram, IN

Key dates

• Filing date: Feb 18, 2020
• Grant date: Apr 5, 2022
• Expiry date: Jul 2, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2209/509
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers. A memory bank arbiter may arbitrate among the accelerators for accessing the memory banks.