Event log tamper resistance
US11295031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are described for generating, by the processor, a first event record in response to an event being performed by the computer and generating, by the processor, a first tamper resistance record in response to the first event record being generated. The first tamper resistance record includes a first signature is created based at least in part on the first event record and a second signature is created based at least in part on the first event record. Aspects also includes validating the first event record based on the first signature and the second signature in the first tamper resistance record in response to a request to detect tampering of the first event record.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.