SRAM with local bit line, input/output circuit, and global bit line
US11295791B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Sep 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.