Multi-chip programming for phased array
US11295828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Apr 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.