Micro semiconductor stacked structure and electronic apparatus having the same
US11296061B2 · kind B2 · utility
0Cited by
0References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A micro semiconductor stacked structure includes at least two stacked structure array units, wherein one stacked structure array unit is stacked on the other stacked structure array unit. In particular, the stacked structure array unit is stacked on the other stacked structure array unit along a vertical direction. Each stacked structure array unit includes a substrate, a conductive pattern layer disposed on the substrate, and a plurality of micro semiconductor devices disposed on the substrate and electrically connected to the conductive pattern layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.