Electrostatic protection circuit and manufacturing method thereof, array substrate and display apparatus
US11296074B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Jul 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An electrostatic protection circuit and a manufacturing method, an array substrate and a display apparatus in field of display technologies are provided. The electrostatic protection includes a first thin film transistor, a second thin film transistor, and an electrostatic protection line; a gate and a second electrode of the first thin film transistor are connected to a signal line, and a first electrode of the first thin film transistor is connected to the electrostatic protection line; a gate and a second electrode of the second thin film transistor are connected to the electrostatic protection line, and a first electrode of the second thin film transistor is connected to the signal line; each thin film transistor is an oxide thin film transistor, a length-width ratio of a channel of each thin film transistor is greater than or equal to a length-width ratio threshold, the length-width ratio threshold being 5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.