Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits

US11296083B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Ye Lu · San Diego, US
• Lixin Ge · San Diego, US
• Kwanyong LIM · Niskayuna, US
• Jun Chen · 林湖乡, CN

Key dates

• Filing date: Mar 6, 2020
• Grant date: Apr 5, 2022
• Expiry date: Mar 6, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/43
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.