Display panel including compensation semiconductor layer disposed closer to driving semiconductor layer than scan line
US11296183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Oct 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1216
Abstract
The present disclosure provides a display panel. In order to reduce a parasitic capacitance that may occur between a data line and a semiconductor layer and a crosstalk caused by the parasitic capacitance, a display panel includes a substrate, a driving thin film transistor on the substrate, including a driving semiconductor layer and a driving gate electrode, a compensation thin film transistor on the substrate, including a compensation semiconductor layer and a compensation gate electrode, a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor, a scan line extending in a first direction on the substrate, and a gate connection line electrically connected to the scan line, which includes the compensation gate electrode, wherein the compensation semiconductor layer is closer to the driving semiconductor layer than the scan line when viewed on a plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.