Cross-clock-domain processing circuit
US11296709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Jun 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cross-clock-domain processing circuit configured to implement data processing between asynchronous clock domains with a relatively low latency. The cross-clock-domain processing circuit includes a jitter filtering circuit and a synchronization circuit. The jitter filtering circuit is configured to: perform jitter filtering on a clock recovered from input data; adjust a jitter-filtered clock phase; and output a processed input data clock as an output data clock to the synchronization circuit. The synchronization circuit is configured to perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.