Patent · US Active

Residue transfer loop, successive approximation register analog-to-digital converter, and gain calibration method

US11296714B2 · kind B2 · utility

0Cited by
7References
17Claims
0Family size

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Key dates

Filing dateMay 12, 2021
Grant dateApr 5, 2022
Priority date
Expiry dateMay 12, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M1/1245
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.