Quasi-volatile memory device with a back-channel usage
US11301172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Oct 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.