Differential mixed signal multiplier with three capacitors
US11301211B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jul 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.