Logical to physical mapping management using low-latency non-volatile memory
US11301369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Oct 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.