Data storage device with wear range optimization
US11301376B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Aug 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device can be arranged with a semiconductor memory having a plurality of erasure blocks accessed by a controller to store data. An access count for each respective erasure block can be generated to allow a wear range for the semiconductor memory to be computed based on the respective access counts with the controller. A performance impact of the wear range is evaluated with the controller in order to intelligently alter a deterministic window of a first erasure block of the plurality of erasure blocks in response to the performance impact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.