Multiple processor computing device with configurable electrical connectivity to peripherals
US11301397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Apr 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device, comprising at least one peripheral computing component, electrically connected to each of a plurality of hardware processors; wherein at least one of the plurality of hardware processors is adapted to executing a code for: configuring the at least one peripheral computing component to access at least one first memory location in a first memory component electrically coupled with a first hardware processor of the plurality of hardware processors via a first electrical connection between the peripheral computing component and the first hardware processor; and configuring the at least one peripheral computing component to access at least one second memory location in a second memory component electrically coupled with a second hardware processor of the plurality of hardware processors via a second electrical connection between the peripheral computing component and the second hardware processor; and wherein the first hardware processor is not the second hardware processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.