Layout-based side-channel emission analysis
US11301608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, machine readable media and systems for simulating the leakage of sensitive data in an integrated circuit, such as cryptographic data or keys, are described. In one embodiment, a method can include the following operations: performing a first dynamic voltage drop (DVD) simulation on a plurality of locations, distributed across an integrated circuit (IC), based on a physical model that specifies physical layout of components on the IC, the IC storing sensitive data in locations of the layout; performing an IC level side channel correlation analysis between each of the locations and the sensitive data based on the results of the first DVD simulation; and selecting, based upon the IC level side channel correlation analysis, a subset of the locations for further simulations to simulate leakage of the sensitive data. Other methods, media and systems are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.