Systems and methods for obfuscating a circuit design
US11301609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jun 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for managing operations for generating a plurality of designs of an integrated circuit chip are described. One of the methods includes receiving a request with a specification of the integrated circuit chip from a requester account, receiving a plurality of requests from a plurality of community member accounts for viewing the specification, and providing access to the specification to the plurality of community member accounts. The method further includes receiving a plurality of instances of the acceptance from the plurality of community member accounts for creating the plurality of designs, providing access to a plurality of resources to the plurality of community member accounts, and receiving a plurality of design files having the plurality of designs from the plurality of community member accounts. The method includes providing access to the plurality of designs to the requester account for approval or disapproval of the plurality of designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.