Method of controlling on-die termination and memory system performing the same
US11302384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jul 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of controlling on-die termination (ODT) in a memory system including a plurality of memory units that shares a data bus to transfer data, ODT circuits of the plurality of memory units are enabled into an initial state, a resistance value of the ODT circuit is set to a first resistance value, of at least one write non-target memory unit among the plurality of memory units during a write operation on a write target memory unit among the plurality of memory units, and a resistance value of the ODT circuit is set to a second resistance value, of at least one read non-target memory unit among the plurality of memory units during a read operation on a read target memory unit among the plurality of memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.