Circuit for reducing leakage current of SRAM memory array and control method for same
US11302389B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Dec 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It discloses a circuit for reducing a leakage current of a static random access memory (SRAM) memory array and a control method for the same. The circuit includes a memory array power supply voltage control module, a memory array ground terminal voltage control module and a memory array. The present invention controls the voltages on the power supply terminal and the ground terminal of the memory array through the memory array power supply voltage control module and the memory array ground terminal control module, and may reduce the actual data retention voltages of the bitcells, thereby reducing the leakage power of the SRAM in a data retention state. Meanwhile, the present invention implements the function of adjusting the data retention voltage values of the bitcells by controlling different adjustment signals to cope with different design requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.