Carrier for back end of line processing
US11302563B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68327
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A carrier assembly is configured to support a wafer, including during back end of line (BEOL) processing. The carrier assembly includes dual carriers. A first carrier includes a stepped structure so as to situate the wafer. A side of the wafer is bonded to the first carrier without adhesive. The first carrier is positioned atop the second carrier, so as to be mechanically supported by the second carrier. Each carrier is made by wet etching of laminated glass, without mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.