Trench shield isolation layer
US11302568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2019 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Sep 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.