Printed circuit board compensation structure for high bandwidth and high die-count memory stacks
US11302645B2 · kind B2 · utility
0Cited by
22References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.