Display device including pad arranged in peripheral area
US11302771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | May 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/38
Abstract
A display device includes a substrate including a display area and a peripheral area outside the display area, a thin-film transistor arranged in the display area, a display element arranged in the display area, an interlayer insulating layer covering the thin-film transistor, a conductive layer arranged above the interlayer insulating layer, a first insulating layer covering the conductive layer, a pad arranged in the peripheral area, and a second conductive layer covering a central portion of the pad. The pad is connected to a connection line through a contact hole, and the connection line is arranged on a same first layer as a gate electrode of the thin-film transistor. A side surface of the pad is covered by the first insulating layer or the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.