In-situ straining epitaxial process
US11302782B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 4, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | May 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/53
Abstract
A semiconductor device includes an epitaxial straining region formed within a semiconductor substrate, the straining region being positioned adjacent to a gate stack, the gate stack being positioned above a channel. The straining region comprises a defect comprising two crossing dislocations such that a cross-point of the dislocations is closer to a bottom of the straining region than to a top of the straining region. The straining region comprises an element with a smaller lattice constant than a material forming the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.