Adaptive voltage scaling methods and systems therefor
US11307244B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present techniques disclose a logic gate for an adaptive voltage scaling monitor, the logic gate comprising an inverting output and further comprising an imbalance between the drive strength of an NMOS component and a PMOS component thereof, and wherein the imbalance is operable to cause a switching delay of the gate to be primarily dependent on one of the NMOS component or the PMOS component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.