Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions
US11307634B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jan 28, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions is disclosed. A power predictor receives, from a power controller that controls voltage and/or frequency of a processor core of a processor device, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction. The power predictor, based on the processor core power quantifier, stores an instruction power level in association with the processor instruction. The power predictor subsequently determines that the processor instruction is to be executed by the processor core at a future point in time. The power predictor accesses the instruction power level previously stored in association with the processor instruction. The power predictor, prior to the processor instruction being executed by the processor core, communicates to the power controller a proposed power level based on the instruction power level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.