Multiple accumulate busses in a systolic array
US11308027B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Oct 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.