Electronic circuit, particularly for the implementation of neural networks with multiple levels of precision
US11308388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Aug 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.