Delay locked loop circuit and semiconductor memory device having the same
US11309002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit and a semiconductor memory device are provided. The delay locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal the feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, to detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and to change a code value in response to the first phase difference detection signal or the second phase difference detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.