Patent · US Active

Gain cell embedded DRAM in fully depleted silicon-on-insulator technology

US11309008B2 · kind B2 · utility

0Cited by

1References

29Claims

0Family size

Assignee

Bar-Ilan University · IL

Inventors

Robert Giterman · Beer Sheva, IL
Adam Teman · Lausanne, CH

Key dates

Filing date	Jul 9, 2019
Grant date	Apr 19, 2022
Priority date	—
Expiry date	Jul 9, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C2211/4016
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An FD-SOI GC-edRAM gain cell includes: The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.