Semiconductor circuit and semiconductor circuit system to suppress disturbance in the semiconductor circuit
US11309025B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.