Memory system that uses NAND flash memory as a memory chip
US11309051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.