Semiconductor memory device and storage device
US11309053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Sep 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.