Chip package structure having a package substrate disposed around a die
US11309227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure and a chip package method, the chip package structure including a die and a package substrate disposed around the die. A solder joint is disposed on a first surface of the die. Remaining surfaces of the die other than a second surface are wrapped by an injection molding material. At least one pair of opposite sides of the package substrate is embedded in the injection molding material. A contact area between the pair of opposite sides and the injection molding material accounts for more than half of a surface area of the pair of opposite sides. The second surface is a surface that is of the die and that is opposite to the first surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.