P-type semiconductor layers coupled to N-type semiconductor layers
US11309349B2 · kind B2 · utility
0Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a P-N junction comprising a monolithic N-type semiconductor layer coupled to a monolithic P-type semiconductor layer. The monolithic N-type semiconductor layer includes a first portion and a second portion. The first portion has a first surface and the second portion has a second surface facing away from the first surface. The monolithic P-type semiconductor layer includes a third portion and a fourth portion. The third portion has a third surface and the fourth portion has a fourth surface facing away from the third surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.