Electrostatic prevention circuit, array substrate and display device
US11309698B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Dec 15, 2017 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jul 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic prevention circuit, an array substrate and a display device are provided. The electrostatic prevention circuit includes an electrostatic prevention sub-circuit, and the electrostatic prevention sub-circuit includes a thin film transistor and a capacitor; a gate electrode of the thin film transistor is connected to the capacitor, and the thin film transistor is controlled by a signal passing through the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.