Level shifting circuit
US11309891B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present application is directed to a level shifting circuit. In one form, a level shifting circuit includes a first inverter, a level shifting unit, and a fast driving unit. The first inverter is configured to invert an input signal received at an input node and to output an inverted input signal to a second input node. The level shifting unit is configured to perform amplitude up-shifting processing on a received input signal. The fast driving unit is configured to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.