Data bus signal conditioner and level shifter
US11309892B2 · kind B2 · utility
1Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2021 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Feb 11, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.