Monitor circuitry for power management and transistor aging tracking
US11309900B2 · kind B2 · utility
1Cited by
1References
17Claims
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Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jun 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01R2201/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.