Bus transceiver with ring suppression
US11310072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Oct 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40215
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.