Verification of instructions from main processor to auxiliary processor
US11314518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Sep 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of monitoring execution in an execution environment of an operation, for example a cryptographic operation, comprising a sequence of instructions, is disclosed. Instructions sent in the sequence from a main processor to one or more auxiliary processors, for example cryptographic processors, to execute the operation are monitored and the sequence of instructions is verified using verification information. The method comprises enabling output from the execution environment of a result of the operation in response to a successful verification of the sequence, or generating a verification failure signal in response to a failed verification of the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.