Systems and methods for optimizing clock distribution in NVMe storage enclosures
US11314666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Sep 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory express (NVMe) based storage system may include a processor; an input/output (I/O) port operatively coupled to a data network; a drive interface board (DIB), including: a PCIe switch communicatively coupled to the processor to receive signals from the processor to a plurality of NVMe storage devices; and a source clock communicatively coupled to the PCIe switch; a connector communicatively coupling the DIB to relay clock signals to a plurality of NVMe drives at a drive mid-plane baseboard; the drive mid-plane baseboard communicatively coupled to the source clock, the drive mid-plane baseboard including: a clock distribution module to receive a source clock signal from the source clock, the clock distribution modules placed at the drive baseboard to distribute the clock signals to the plurality of NVMe storage devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.