Low noise serial interfaces with gated clock
US11314685B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.