Gate driver and display panel having the same
US11315459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel includes pixels connected to gate lines, and a gate driver that supplies a gate signal to at least one of the gate lines and includes a plurality of stages. Each stage includes a pull-up transistor to apply a turn-on voltage of a first clock signal to an output terminal responsive to a voltage at a Q-node, a pull-down transistor to apply a turn-off voltage to the output terminal responsive to a voltage at a QB-node that holds the turn-on voltage during a period in which the output terminal is applied the turn-off voltage, and a QB-node control unit to apply the turn-on voltage to the QB-node responsive to the first clock signal and a second clock signal in reverse-phase with the first clock signal. Accordingly, a display panel may include a gate driver that can set, reset, and hold the voltage at a QB-node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.