GOA circuit and display panel thereof
US11315512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driver on array (GOA) circuit is provided. The GOA circuit includes a plurality of cascading GOA units. One of the GOA unit includes: a scan control module, an anti-backfill module connected to a constant high-level signal and the scan control module, a cascading reset module, and a gate signal output module. Base on functions of prior art solution, the provided GOA circuit of the disclosure reduces two types of signal to simplify signal traces at the bezel to realize a narrow bezel design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.