Adaptive erase voltage based on temperature
US11315637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.