Pattern design for integrated circuits and method for inspecting the pattern design for integrated circuits
US11315841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A pattern design for defect inspection, the pattern design including a first floating conductive line; a second floating conductive line; and a grounded conductive line disposed between the first floating conductive line and the second floating conductive line. The first floating conductive line, the second floating conductive line, and the grounded conductive line are divided into a main pad region, a plurality of subregions, a plurality of sub-pad regions, and a ground region. The main pad region is positioned at a first end portion of the pattern design. The ground region is positioned at a second end portion of the pattern design. The plurality of subregions and the plurality of sub-pad regions are positioned between the main pad region and the ground region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.