Semiconductor package having stiffener
US11315849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Oct 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.